24 lines
1.3 KiB
TeX
24 lines
1.3 KiB
TeX
\acrodef{bcb}[BCB]{\techterm{Bound Check Bypass}}
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\acrodef{bhb}[BHB]{\techterm{Branch History Buffer}}
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\acrodef{bpu}[BPU]{\techterm{Branch Prediction Unit}}
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\acrodef{btb}[BTB]{\techterm{Branch Target Buffer}}
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\acrodef{bti}[BTI]{\techterm{Branch Target Injection}}
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\acrodef{cp}[CP]{\techterm{Cross Privilege}}
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\acrodef{eibrs}[eIBRS]{\techterm{Enhanced Indirect Branch Restricted Speculation}}
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\acrodef{ibpb}[IBPB]{\techterm{Indirect Branch Prediction Barrier}}
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\acrodef{ibrs}[IBRS]{\techterm{Indirect Branch Restricted Speculation}}
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\acrodef{isa}[ISA]{\techterm{Instruction Set Architecture}}
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\acrodef{llc}[LLC]{\techterm{Last-Level Cache}}
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\acrodef{mmu}[MMU]{\techterm{Memory Management Unit}}
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\acrodef{pa}[PA]{\techterm{Physical Address}}
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\acrodefplural{pa}{\techterm{Physical Addresses}}
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\acrodef{pc}[PC]{\techterm{Program Counter}}
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\acrodef{pf}[PF]{\techterm{Page Fault}}
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\acrodef{rsb}[RSB]{\techterm{Return Stack Buffer}}
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\acrodef{smap}[SMAP]{\techterm{Supervisor Mode Access Prevention}}
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\acrodef{smep}[SMEP]{\techterm{Supervisor Mode Execution Prevention}}
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\acrodef{smt}[SMT]{\techterm{Simultaneous Multithreading}}
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\acrodef{utk}[U $\to$ K]{\techterm{User} $\to$ \techterm{Kernel}}
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\acrodef{va}[VA]{\techterm{Virtual Address}}
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\acrodefplural{va}{\techterm{Virtual Addresses}}
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